Many computing systems can include components and/or sub-systems that operate on different clock frequencies and that have different data bus bit sizes. For example, a computing system may include a processor that operates at a higher clock frequency than a system bus master. And, the same computing system may have a system bus that has a larger bit size than its processor bus. In this example computing system, both the processor and the components connected to the system bus will need access to some amount of computer memory. Because or the differences in clock frequency and bus size, the processor and system bus master may need different computer memories operating in accordance with their respective clock frequency and bus size. However, use of multiple memory devices operating in accordance with different clock frequencies and bus sizes adds expense and complexity to the computing system. Therefore, it is of interest that both the processor and the system bus master be able to utilize a common shared memory device, despite their differences in clock frequency and bus size. It is within this context that the present invention arises.